1. Field of the Invention
This invention relates to yield analysis of a semiconductor process and, in particular, to semiconductor process yield analysis in which the relationship between a die-level parameter and a wafer-level parameter is evaluated.
2. Related Art
Electronic devices are commonly constructed using one or more integrated circuit chips. Each integrated circuit chip is a semiconductor die that has been appropriately processed to produce desired electrical circuitry thereon. Typically, multiple semiconductor die are defined on a single semiconductor substrate (“wafer”) and processed together at one time to produce multiple integrated circuit chips. The processing of a semiconductor wafer to produce integrated circuit chips is typically very complex, often involving hundreds of processing steps. Consequently, it is not uncommon for a processed wafer to include one or more die that are determined to be defective in some way and unfit for use as an integrated circuit chip in an electronic device. It is an ongoing concern of the semiconductor processing industry to increase the yield (i.e., the percentage of usable die on each processed wafer) of semiconductor process. Increasing semiconductor process yield can be facilitated by performing yield analysis that is intended to identify defect(s) produced by a semiconductor process and/or the source of defect(s) produced by a semiconductor process.
Previously, one way in which yield analysis has been accomplished is by performing parametric tests (“die-level parametric tests”) on the semiconductor die that produce information regarding the performance of the die during operation of the circuitry formed thereon and performing parametric tests (“wafer-level parametric tests”) at other specified test locations on the semiconductor wafer that produce information regarding the structure of the wafer and/or the function of “test electrical components” formed on the wafer, then evaluating the wafer-level parametric data and die-level parametric data to determine the nature of the relationship (e.g., the existence of a correlation) between the corresponding wafer-level parameter and die-level parameter. Die-level parametric tests can include, for example, tests to determine characteristics of die operation such as electrical noise production, power consumption, heat production, output levels, offsets and frequency responses. Wafer-level parametric tests) can include, for example, tests to determine line width, oxide layer thickness or dopant concentration. Wafer-level parametric tests can also include, for example, tests to determine the electrical characteristics (e.g., resistivity, conductivity, gain, sheet resistance, transistor beta, FET threshold voltage) of a “test electrical component” formed on a wafer. There are many types of die-level parametric tests (more than 800 commonly used types) and wafer-level parametric tests (more than 400 commonly used types), as known to those skilled in the art. As can be appreciated, then, evaluating the relationships between various pairs of wafer-level and die-level parameters can be a time-consuming task.
FIGS. 1A, 1B and 1C illustrate how die-level parametric tests and wafer-level parametric tests can be performed on a semiconductor wafer. In FIG. 1A, multiple stepper fields (a representative one of which is indicated by the numeral 101) are defined on a semiconductor wafer 100 by scribe lanes (a representative one of which is indicated by the numeral 102). (The scribe lanes 102 are sometimes referred to as “frame outline scribe lanes.”) Each stepper field 101 represents an area which is processed at one time by equipment used to effect the steps in a semiconductor process. FIG. 1B shows an area of the wafer 100 in more detail. Within each stepper field 101, multiple die (a representative one of which is indicated by the numeral 103) are defined by additional scribe lanes (a representative one of which is indicated by the numeral 104). (The scribe lanes 104 are sometimes referred to as “intra-frame scribe lanes.”) As can be seen in FIG. 1B, contact pads (a representative one of which is indicated by the numeral 103a) are formed on the die 103 which enable electrical connection to be made from the die 103 to testing apparatus that is used to perform die-level parametric tests. FIG. 1C shows in more detail an intersection of two scribe lanes 104 illustrated in FIG. 1B. As can be seen in FIG. 1C, electrical components (a representative one of which is indicated by the numeral 104a), such as, for example, resistors, capacitors and transistors, are formed in the scribe lanes 104. (A collection of electrical components 104a in a scribe lane or stepper field is sometimes referred to as a “scribe lane monitor.”) Wafer probe apparatus can be used to perform wafer-level parametric tests on the electrical components 104a in the scribe lanes 104. (Wafer-level parametric tests can also be performed on electrical components formed in special designated areas of a semiconductor wafer.)
Previous methods of accomplishing yield analysis by evaluating wafer-level and die-level parametric data to determine the nature of the relationship between the corresponding wafer-level and die-level parameters are deficient in certain respects. For example, previously, parametric tests have been performed for all regions of a semiconductor wafer. The increased use of 12″ wafers and reduced use of 6″ wafers has made such an approach inordinately time consuming (e.g., as much as 20 hours per wafer); moreover, this problem is exacerbated by the typical need to perform parametric tests on multiple (e.g., 5 or more) wafers in order to evaluate parametric relationships. Additionally, testing all regions of a semiconductor wafer (and combining and averaging parametric data from all of those regions) can cause the influence of regions including bad die, which are of most use in evaluating parametric relationships, to be undesirably diluted in such evaluation, in particular to a point that causes relationships that would otherwise be identified to go unnoticed. Further, when all regions of a semiconductor wafer are tested, normally present geometric patterns in parametric values are more likely to obscure or confound relationships that would otherwise be identified.
A previous method of accomplishing yield analysis by evaluating parametric data to determine the nature of the parametric relationships has also been performed by obtaining parametric data for multiple semiconductor wafers at the same locations for each wafer. This method advantageously reduces the time required for performing the yield analysis. Parametric data is obtained at the same locations for each wafer to avoid the need to reprogram the stepper machine (i.e., the apparatus that effects testing at different locations on a wafer) to obtain parametric data for each new wafer. However, since parametric data is obtained at the same locations on each wafer, parametric data of most use in identifying parametric relationships may not be considered in the analysis, which may result in parametric relationships being overlooked that would otherwise be identified.
Previous methods of accomplishing yield analysis by evaluating the relationship between a die-level parameter and a wafer-level parameter have sometimes arranged die-level parametric data and corresponding wafer-level parametric data into groups, determined an average value of the die-level parametric data and corresponding wafer-level parametric data for each group, then used the average values to evaluate the relationship between the die-level parameter and wafer-level parameter exists. Such previous methods have grouped the parametric data into 3 groups. However, the use of 3 groups may not provide a sufficiently detailed summary of the parametric data to enable adequate evaluation of the nature of the relationship between two parameters, e.g., may not provide enough data values to produce a sufficiently accurate curve fit representing the expected relationship between two parameters.
Additionally, a previous such method of accomplishing yield analysis has discarded extreme values (high and/or low) of the parametric data before arranging the die-level parametric data and corresponding wafer-level parametric data into groups. However, such filtering of the parametric data may disadvantageously discard parametric data than can be important in accurately evaluating the relationship between a die-level parameter and a wafer-level parameter.
Finally, previous methods of accomplishing yield analysis by evaluating the relationship between a die-level parameter and a wafer-level parameter based on a grouping of the parametric data have been implemented using a single grouping of the parametric data (the parametric data are arranged into groups based on the values of the wafer-level parametric data). The use of a single grouping of the parametric data in evaluating the relationship between a die-level parameter and a wafer-level parameter may sometimes produce misleading results, e.g., may result in a “false-positive” indication of a correlation between the die-level parameter and the wafer-level parameter.